{ "disks": { "1": { "dirs": [ { "path": "/", "files": [ { "name": "403122 PLD", "size": 704, "date": "1991-03-19", "time": "10:18" }, { "name": "450877 PLD", "size": 819, "date": "1991-08-11", "time": "12:07" }, { "name": "450883 PLD", "size": 1395, "date": "1991-08-11", "time": "12:09" }, { "name": "450888 PLD", "size": 1000, "date": "1991-08-11", "time": "11:37" }, { "name": "450895 PLD", "size": 891, "date": "1991-08-11", "time": "11:44" }, { "name": "450896 PLD", "size": 874, "date": "1991-08-11", "time": "11:42" }, { "name": "450898 PLD", "size": 1018, "date": "1991-08-11", "time": "12:00" }, { "name": "450899 PLD", "size": 1018, "date": "1991-08-11", "time": "11:50" }, { "name": "450900 PLD", "size": 1246, "date": "1991-08-11", "time": "11:48" }, { "name": "450901 PLD", "size": 1276, "date": "1991-08-11", "time": "11:54" }, { "name": "450902 PLD", "size": 1237, "date": "1991-08-11", "time": "11:40" }, { "name": "450903 PLD", "size": 1005, "date": "1991-08-11", "time": "12:05" }, { "name": "450904 PLD", "size": 945, "date": "1991-08-11", "time": "12:02" }, { "name": "450905 PLD", "size": 994, "date": "1991-08-11", "time": "11:53" }, { "name": "450906 PLD", "size": 828, "date": "1991-08-11", "time": "11:52" }, { "name": "451318 PLD", "size": 754, "date": "1991-08-11", "time": "11:55" }, { "name": "451319 PLD", "size": 950, "date": "1991-08-11", "time": "11:45" }, { "name": "451320 PLD", "size": 1299, "date": "1991-08-11", "time": "12:10" }, { "name": "451321 PLD", "size": 1040, "date": "1991-08-11", "time": "11:36" }, { "name": "451322 PLD", "size": 1221, "date": "1991-08-11", "time": "11:57" }, { "name": "454233 PLD", "size": 1133, "date": "1991-08-11", "time": "11:58" }, { "name": "454365 PLD", "size": 1750, "date": "1991-08-11", "time": "12:04" }, { "name": "454920 PLD", "size": 1137, "date": "1991-08-11", "time": "11:38" }, { "name": "456402 PLD", "size": 772, "date": "1991-08-11", "time": "15:24" }, { "name": "4L8 PLD", "size": 542, "date": "1991-01-30", "time": "14:04" }, { "name": "ADDER PLD", "size": 1738, "date": "1991-12-08", "time": "14:58" }, { "name": "BARREL22 PLD", "size": 1895, "date": "1991-12-08", "time": "14:58" }, { "name": "BUSARB PLD", "size": 4598, "date": "1991-12-08", "time": "14:58" }, { "name": "CBLD EXE", "size": 29878, "date": "1991-12-08", "time": "14:56" }, { "name": "CONFIG SYS", "size": 23, "date": "1992-08-02", "time": "10:08" }, { "name": "COUNT10 PLD", "size": 2443, "date": "1991-12-08", "time": "14:58" }, { "name": "COUNT13 PLD", "size": 3332, "date": "1991-12-08", "time": "14:58" }, { "name": "COUNT8 PLD", "size": 2538, "date": "1991-12-08", "time": "14:58" }, { "name": "COUNT8A PLD", "size": 2628, "date": "1991-12-08", "time": "14:58" }, { "name": "CSIM EXE", "size": 15244, "date": "1991-12-08", "time": "14:55" }, { "name": "CSIMA EXE", "size": 83120, "date": "1991-12-08", "time": "14:56" }, { "name": "CUP BAT", "size": 65, "date": "1992-06-21", "time": "17:42" }, { "name": "CUPL DL", "size": 311295, "date": "1991-12-08", "time": "14:58" }, { "name": "CUPL EXE", "size": 16369, "date": "1991-12-08", "time": "14:53" }, { "name": "CUPLA EXE", "size": 78597, "date": "1991-12-08", "time": "14:53" }, { "name": "CUPLB EXE", "size": 115879, "date": "1991-12-08", "time": "14:54" }, { "name": "CUPLC EXE", "size": 57845, "date": "1991-12-08", "time": "14:54" }, { "name": "CUPLM EXE", "size": 163408, "date": "1991-12-08", "time": "14:55" }, { "name": "CUPLX EXE", "size": 23226, "date": "1991-12-08", "time": "14:53" }, { "name": "DATASEP PLD", "size": 3349, "date": "1991-12-08", "time": "14:58" }, { "name": "DECADE PLD", "size": 2604, "date": "1991-12-08", "time": "14:58" }, { "name": "FLOPS PLD", "size": 2408, "date": "1991-12-08", "time": "14:58" }, { "name": "GATES PLD", "size": 1580, "date": "1991-12-08", "time": "14:58" }, { "name": "HEXDISP PLD", "size": 2671, "date": "1991-12-08", "time": "14:58" }, { "name": "IODECODE PLD", "size": 1891, "date": "1991-12-08", "time": "14:58" }, { "name": "IOPORT PLD", "size": 2411, "date": "1991-12-08", "time": "14:58" }, { "name": "KEYBOARD PLD", "size": 9039, "date": "1991-12-08", "time": "14:58" }, { "name": "LOOKUP PLD", "size": 2307, "date": "1991-12-08", "time": "14:58" }, { "name": "MDECODE PLD", "size": 2081, "date": "1991-12-08", "time": "14:58" }, { "name": "MULTIBUS PLD", "size": 4266, "date": "1991-12-08", "time": "14:58" }, { "name": "PALASM OPR", "size": 90, "date": "1991-12-08", "time": "14:56" }, { "name": "PRIORITY PLD", "size": 2557, "date": "1991-12-08", "time": "14:59" }, { "name": "PTOC EXE", "size": 21381, "date": "1991-12-08", "time": "14:56" }, { "name": "README", "size": 11280, "date": "1991-12-08", "time": "14:54" }, { "name": "RIPPLE8 PLD", "size": 2007, "date": "1991-12-08", "time": "14:59" }, { "name": "SHFTCNT PLD", "size": 2643, "date": "1991-12-08", "time": "14:59" }, { "name": "SHFTCNT4 PLD", "size": 2100, "date": "1991-12-08", "time": "14:59" }, { "name": "SHFTCNT6 PLD", "size": 2646, "date": "1991-12-08", "time": "14:59" }, { "name": "STEPPER PLD", "size": 5884, "date": "1991-12-08", "time": "14:59" }, { "name": "TCOUNTER PLD", "size": 4971, "date": "1991-12-08", "time": "14:59" }, { "name": "TMPL PLD", "size": 2340, "date": "1991-12-08", "time": "14:59" }, { "name": "WAITGEN PLD", "size": 2037, "date": "1991-12-08", "time": "14:59" }, { "name": "WGTTL PLD", "size": 1705, "date": "1991-12-08", "time": "14:59" } ] } ] } }, "desc_file": "README", "desc_text": "\r\nRelease Notes for CUPL - Universal Compiler for Programmable Logic\r\n\r\nCUPL Release\r\nVersion Date NOTES\r\n-----------------------------------------------------------------------\r\n1.01a 9/10/83 First production release of CUPL with universal\r\n design support for 29 devices.\r\n\r\n1.01b 10/31/83 Fixes for various devices including M16C1 and\r\n N16C1. Fix in CSIM to simulate 16 product\r\n terms in PAL16C1. Distribute on double-sided\r\n diskettes (MS/PC-DOS).\r\n\r\n2.00a 11/19/84 First release of newly structured CUPL, using\r\n device database with support for 76 devices.\r\n Added support for PAL XOR devices, IFL JK and RS\r\n devices. Improved simulator handling of\r\n asynchronous feedback. Many new syntax features\r\n including outputs grouped as fields, numbers,\r\n and function table input. Added full logic\r\n minimization.\r\n\r\n2.01a 12/21/84 Restructuring of distribution diskettes for\r\n proper installation (MS/PC-DOS). CSIM properly\r\n removes existing vectors in JEDEC file before\r\n appending new test vectors. CSIM properly renames\r\n JEDEC file when $exit directive used. CSIM\r\n properly simulates programmable polarity before\r\n the output register.\r\n\r\n Added support for: AMD AmPAL18P8\r\n MMI PAL6L16\r\n MMI PAL8L14\r\n Device changes:\r\n ---------------\r\n p16rp4 rev 11 Fix for simulation of\r\n p16rp6 rev 11 programmable polarity before\r\n p16rp8 rev 11 output register.\r\n p32r16 rev 06 MMI changed JEDEC fuse spec.\r\n p64r32 rev 06 MMI changed JEDEC fuse spec.\r\n f103 rev 07 Fixed polarity of output pins.\r\n f155 rev 08 Fixed HL plot for register\r\n f157 rev 07 RESET/PRESET & Complement\r\n f159 rev 12 array. Fixed polarity of\r\n non-registered output pins.\r\n f162 rev 04 Fixed polarity of output pins.\r\n f163 rev 04 Fixed polarity of output pins.\r\n p20rs4 rev 16 Fix for simulation of\r\n p20rs8 rev 14 programmable polarity before\r\n p20rs10 rev 15 output register.\r\n\r\n2.02a 1/17/85 Incorporates faster, more memory efficient\r\n algorithm for DeMorgan property.\r\n\r\n Added support for: MMI PAL20RA10\r\n MMI PAL20P8E\r\n Device changes:\r\n ---------------\r\n p16rp4 rev 11 Fix for simulation of\r\n p16rp6 rev 11 programmable polarity before\r\n output register.\r\n\r\n2.02b 3/20/85 Fixes for various devices. Clarify certain error\r\n messages. Made -g flag work. Added out of memory\r\n error message for logic minimizer. Improved CSIM\r\n error reporting.\r\n\r\n Device changes:\r\n ---------------\r\n ep300 rev 15 Added warnings for SP/AR terms.\r\n Fixed polarity for pin 1.\r\n p20ra10 rev 08 Fixed simulation error on pin 20.\r\n p20rs4 rev 17 Fixed number of fuses in JEDEC.\r\n p20s10 rev 14 Fixed number of fuses in JEDEC.\r\n p32r16 rev 09 No functional change.\r\n p64r32 rev 12 Allow pin 44 to be input.\r\n Allow combinatorial output mode.\r\n f155 rev 10 Fixed HL plot for complement\r\n f157 rev 09 array.\r\n f159 rev 15 Fixed HL plot for complement\r\n array and output enable terms.\r\n Fixed default for pin 6 to be\r\n active when used as an output.\r\n f105 rev 15 Fixed HL plot for complement\r\n f167 rev 15 array. Allow AP extension\r\n on internal node flip-flops.\r\n\r\n2.02c 5/30/85 Fixed ASCII-HEX generation for PROMs.\r\n\r\n Device changes:\r\n ---------------\r\n p20p8e rev 02 Fixed polarity for output pins.\r\n\r\n2.10a 3/11/86 Added state machine syntax for all registered\r\n devices. Added user defined functions and new truth\r\n table format. Improved logic minimization and\r\n DeMorgan algorithms. Time/date stamp on all output\r\n files. Print chip diagram in documentation file.\r\n Fixed fuse plot generation for FPLA (Signetics)\r\n devices when product terms merged. Use up to 640K \r\n on MS/PC-DOS version.\r\n\r\n Added support for: Altera EP600 (limited)\r\n Lattice GAL16V8, GAL20V8\r\n MMI PAL16RA8\r\n National PL1016P8, PL10016P8\r\n National PL1016RP8, PL10016RP8\r\n Panatech EPL10P8, EPL12P6\r\n Ricoh EPL14P2, EPL16P8\r\n VTI EPL16RP4, RP6, RP8\r\n Signetics 82S151, 82S168\r\n Signetics 82S173, 82S179\r\n T.I. PLR19L8, PLR19R4\r\n T.I. PLR19R6, PLR19R8\r\n T.I. FPGA529\r\n\r\n Device changes:\r\n ---------------\r\n f157 rev 13 Fixed HL plot for bank A reset and\r\n preset terms.\r\n f162 rev 07 Signetics changed JEDEC fuse spec.\r\n f163 rev 07 Signetics changed JEDEC fuse spec.\r\n p14p4 rev 07 Fixed error in fuse map.\r\n p20rs10 rev 19 Fixed output enable for pin 14.\r\n p1020p8 rev 06 Created from p20p8e when MMI\r\n changed pinout.\r\n\r\n2.11a 7/15/86 Allows use of floppy diskettes for MS-DOS systems.\r\n CUPL looks at search path for each module. Allows \r\n larger state machine designs. Fixes in expression \r\n evaluation and logic minimization. Added multiple \r\n output minimization for FPLA (Signetics) devices. \r\n Added support for latched input devices and\r\n toggle flip-flops.\r\n\r\n Added support for: AMD AmPAL23S8\r\n T.I. PLT19L8, PLT19R4\r\n T.I. PLT19R6, PLT19R8\r\n T.I. TIBPAL20SP8\r\n\t\t\t\t\t T.I. TIBPAL20RSP4\r\n T.I. TIBPAL20RSP6\r\n\t\t\t\t\t T.I.\t TIBPAL20RSP8\r\n T.I. TIBPAL22VP10\r\n\r\n Device changes:\r\n ---------------\r\n ep300 rev 20 Added new macrocells for schematic\r\n f105 rev 21 capture.\r\n f155 rev 14 \r\n f157 rev 14 \r\n f159 rev 19 \r\n f167 rev 22 \r\n f168 rev 04 \r\n f179 rev 02 \r\n p16ra8 rev 02 \r\n p20ra10 rev 13\r\n p19r4r rev 06\r\n p19r6r rev 06\r\n p19r8r rev 06\r\n p19l8r rev 07 Fixed error in fuse plot. Fixed\r\n input pin 2 error.\r\n\t\t\tep600\t rev 05\t Fixed error in fuse map. Added \r\n support for T flip-flops and\r\n asynchronous register clocking.\r\n\t\t\tg20v8ma rev 02 Fixed error in fuse map for pin 15.\r\n\r\n2.11b 11/14/86 Fixes for indexed variables in state machine \r\n syntax and CSIM ORDER list. Added the QV and P\r\n fields to the JEDEC file when test vectors are\r\n created. Added an alternate packages device\r\n library, SMD.DL, which has leadless chip carrier\r\n pinouts for 24 pin DIPs in 28 pin LCCs.\r\n\r\n Added support for: AMD AmPAL10H20EV8 \r\n AMD AmPAL10H20EG8 \r\n AMD AmPAL22P10\r\n AMD AmPAL22RP4\r\n AMD AmPAL22RP6\r\n AMD AmPAL22RP8\r\n AMD AmPAL22RP10\r\n\t\t\t\t\t MMI\t PAL10H20G8\r\n T.I. TIBPAL16SP8\r\n\t\t\t\t \t T.I. TIBPAL16RSP4\r\n T.I. TIBPAL16RSP6\r\n\t\t\t\t\t T.I.\t TIBPAL16RSP8\r\n\r\n Device changes:\r\n ---------------\r\n p16ra8 rev 03 Fixed error in fuse map. \r\n ep600 rev 10 Fixed asynchronous reset defaults\r\n and simulation" }